1. Field of the Invention
The present invention relates to the delaying of clock signals using delayed signal generators, which may detect, create or interpolate delayed clock signals. The delayed clock signals may include a delay in a clock signal cycle.
2. Description of the Related Art
A poly-phase clock generator which utilizes a PLL (Phase Lock Loop) may extract signals from a VCO (Voltage Controlled Oscillator) that are phase locked by a phase of π/2, for example. FIG. 8A is a block diagram illustrating a conventional poly-phase clock generator utilizing a PLL. FIG. 8B is a timing diagram illustrating the input/output signals, which correspond to the input/output signals illustrated in the VCO of FIG. 8A. Referring to FIGS. 8A and 8B, if for example clock signal P0 is locked up with clock reference signal fref, the VCO may extract phases from P1, P2 and P3. FIG. 8B illustrates P0 having a phase cycle opposite from P0. P1 for example, may be delayed by a phase difference of π/2 compared to fref, and P3 may have a phase cycle opposite of P1.
A poly-phase clock generator utilizing a PLL may have certain advantages and disadvantages over a traditional PLL, depending upon the circuit configuration constructed to include the PLL. An advantage of using a poly-phase clock generator may include the removal of jitter. However, the poly-phase clock generator may have certain disadvantages. A first disadvantage may be the storage of unwanted jitter resulting from a closed loop configuration of the VCO. A second disadvantage of using a poly-phase clock signal generator may be the need for an analog circuit including a capacitor that uses a charge pump, and thus may not include a single integrated chip. In an attempt to compensate for the disadvantages that may be present when using a poly-phase clock generator, an increase in the dimensions, operation speed and power consumption of a corresponding circuit configuration may be required.
Another disadvantage that may be presented when using a poly-phase clock generator is the multiple clock cycles that may be required when attempting to lock onto a phase. Requests made for clock cycles to lock phase may require tens to hundreds of clock cycles before a phase is locked. Obtaining multiple clock cycles may require the clock signal generator change power levels promptly depending on the number of clock cycles required to lock phase.
A poly-phase clock signal generator may utilize a DLL (Delayed Locked Loop) instead of a PLL. The operation of the DLL may be similar to the PLL when used in a poly-phase clock signal generator, for example the DLL may include using a phase locked at 90 /2 similar to the PLL configuration, and a VCDL (Voltage Controlled Delay Line) which extracts poly-phase clock signals, as show in FIG. 9. Conversely, there may be differences between a poly-phase clock signal generator which utilizes a DLL instead of a PLL.
FIG. 9 is a block diagram illustrating a poly-phase clock signal generator employing a conventional DLL.
A VCDL may include a voltage regulator which delays a phase cycle output of the VCDL up to a phase of 90 /2, and may also extract signals from the output. As a result, if signals are extracted from a DLL, there may be certain advantages of a DLL when compared to a PLL which utilizes an analog circuit. For example, the DLL may use an open loop VCDL which is different from a closed loop VCO. The open loop VCDL may not have to store the phase error that a closed loop VCO would store, thus a more stable system may be obtained.
The clock generator that may be used in a digital DLL may have smaller dimensions, and thus may require less operation voltage than a PLL clock generator. However, a poly-phase clock signal generator which utilizes a DLL configuration may be subject to input jitter, and duty error associated with processing clock signals, and may require multiple clock cycles in order to lock a phase, similar to the PLL configuration.